Power factor correction technologies are widely used in power converters. FIG. 1 schematically shows a typical PFC circuit 50 in the prior art. As shown in FIG. 1, the PFC circuit 50 comprises: a rectifier bridge 51, an EMI capacitor CIN and a boost converter 52, wherein the boost converter 52 includes an energy storage component L, a power switch S, a diode D and a capacitor C connected as shown. An input AC voltage VAC is rectified to a DC voltage through the rectifier bridge 51. A peak value of a current flowing through the energy storage component L is controlled to follow the input AC voltage (i.e., the envelop of the current flowing through the energy storage component is controlled to follow the input AC voltage) by the boost converter 52, so as to convert the DC voltage to a regulated voltage VO.
In order to reduce the size of the energy storage component L, prior art uses a clamp circuit to limit the peak value of the current flowing through the energy storage component in boundary mode, with reference to FIG. 2. The higher the clamp ratio (the ratio of the original peak value of the envelop and the clamped value), the higher the reduction of the size of the energy storage component, but the worse the total harmonic distortion (THD) and the power factor (PF). If the clamp ratio is kept constant, the THD would maintains constant as the input AC voltage goes from low to high, but the PF would worsen when the input AC voltage is high due to the phase shifting caused by the EMI capacitor CIN.